1. Field of the Invention
The present invention relates to a method and apparatus for extracting information of a parasitic element which is generated in automatic placement of devices and automatic routing of wires performed in the design of a semiconductor circuit, and more particularly to a parasitic element extracting apparatus and a parasitic element extracting method in which information of a parasitic element of a semiconductor circuit is extracted from a layout of a semiconductor circuit including a wiring area of a low wire congestion on the assumption that dummy wire (hereinafter, called fill-metal) is arranged in the wiring area in which it is expected to arrange the fill-metal to smoothly perform chemical mechanical polishing.
2. Description of Related Art
As semiconductor apparatuses develop in recent years, it is desired that devices of each semiconductor apparatus are more integrated in the high density. Therefore, it is required that wiring patterns are minutely formed in manufacturing processing. In general, when devices of a semiconductor apparatus are highly integrated in the high density, a multi-layered wiring structure is formed in the semiconductor apparatus. In this multi-layered wiring structure, a plurality of wiring layers separated from each other through insulation films are arranged on a substrate of the semiconductor apparatus, and wires are arranged on each wiring layer. Each wiring layer is minutely patterned with a pattern mask in an exposure step of the manufacturing processing to precisely arrange wires on the wiring layer. Therefore, in cases where the substrate surface, on which the pattern mask is arranged, is not flat because of unevenness of the substrate surface, resolution of the patterning in the exposure step is lowered, and there is a problem that each wiring layer cannot be minutely patterned.
To avoid this problem, the substrate surface is flattened by performing chemical mechanical polishing. This chemical mechanical polishing is generally performed to remove the global unevenness of the substrate surface. In the chemical mechanical polishing, a polishing material flows into a polishing cloth arranged on the substrate surface, and the substrate surface is polished by using the polishing cloth with the polishing material. When the multi-layered wiring structure is formed in a semiconductor apparatus, a lower wiring layer is flattened according to the chemical mechanical polishing, and the exposure step is performed to produce an upper wiring layer on the lower wiring layer. Therefore, wires can be minutely formed on each wiring layer.
However, when a difference in wire congestion between wiring areas of a wiring layer is large, it is difficult to precisely flatten the surface of the wiring layer according to the chemical mechanical polishing. Therefore, to reduce the difference in the wire congestion of the wiring layer, fill-metal denoting dummy wire is inserted in the wiring area of a low wire congestion so as to make degrees of wire congestion in the wiring areas of the wiring layer agree with each other. Here, the wire congestion (or the degree of wire congestion) is defined as a value which is obtained by dividing the number of wires required in a unit lattice of a layout of a semiconductor circuit, in which wiring is roughly performed, by the number of wires which are possible to be arranged in the unit lattice of the layout of the semiconductor circuit. For example, in cases where the unit lattice denotes a square in which each side has a length equal to ten times of a wiring pitch, the number of wires possible to be arranged in the unit lattice is equal to 100. Therefore, in cases where the number of wires required for each unit lattice is equal to 100, the wire congestion is 100%.
Also, each group of integrated devices of a semiconductor circuit, which is different from individual devices, is placed in a separated area and is surrounded by an insulation film to be electrically separated from other groups of integrated devices of the semiconductor circuit, and the integrated devices of the group are connected with each other by using wires formed in a film shape to produce a circuit of the devices. In this case, parasitic elements such as wiring capacitance (or parasitic capacitance) existing between wires and parasitic inductance are parasitically formed in the separation area and the filmed wires of the integrated circuit.
Therefore, to determine the performance of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed in the design processing, it is required to consider an adverse influence of the parasitic elements generated in the semiconductor circuit.
FIG. 10 is a block diagram schematically showing the configuration of a conventional parasitic element extracting apparatus in which information of a parasitic element is extracted from a layout of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed. In FIG. 10, 100 indicates layout information of a semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed. 101 indicates a parasitic element extracting unit for extracting information of a parasitic element from the layout information 100 of the semiconductor circuit. The operation of the parasitic element extracting unit 101 is performed by executing a program, which is prepared from data used to determine the layout of the semiconductor circuit, in a computer. 102 indicates the information of the parasitic element extracted from the layout of the semiconductor circuit by the parasitic element extracting unit 101.
Next, an operation of the conventional parasitic element extracting apparatus is described.
When layout information 100 of the semiconductor circuit, in which the automatic placement of devices and the automatic routing of wires are performed, is received in the parasitic element extracting unit 101, data used to determine the layout of the semiconductor circuit is extracted from the layout information 100. Thereafter, positions of pins, routes of wires used to connect the pins with each other and positions of constituent elements (for example, layers and via holes) of the semiconductor circuit are determined according to the data, and a positional relationship of the constituent elements and sizes of the constituent elements are determined. Thereafter, in the parasitic element extracting unit 101, information 102 of parasitic capacitance and parasitic inductance accompanying each constituent element is extracted from the layout information 100 of the semiconductor circuit according to the positional relationship of the constituent elements and the sizes of the constituent elements.
Thereafter, the information 102 of each parasitic element extracted in the parasitic element extracting unit 101 is related to the constituent element accompanied by the parasitic element for each constituent element, and the information 102 of the parasitic elements related to each constituent element is output. The information 102 of the parasitic elements is used to determine the performance of the semiconductor circuit. Also, the information 102 of the parasitic elements is used to change the design of the semiconductor circuit so as to reduce an adverse influence of the parasitic elements.
Because the conventional parasitic element extracting apparatus has the above-described configuration, the information 102 of the parasitic elements can be extracted from the layout information 100 of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed. However, because influence of fill-metal inserted in the semiconductor circuit in the manufacturing processing of the semiconductor circuit is not considered, there is a problem that an expected performance of the semiconductor circuit cannot be actually obtained because of a parasitic element generated between the fill-metal and a wire really arranged.
This problem is described more precisely below.
In cases where fill-metal denoting dummy wire is, for example, arranged in a wiring area of a low wire congestion in a wiring layer of a semiconductor circuit to flatten the surface of the wiring layer according to the chemical mechanical polishing, a value of capacitance (or a parasitic element) parasitically generated between wires adjacent to each other is increased, and a time delay in a wire really arranged is increased because of the parasitic element. Therefore, the semiconductor circuit cannot be operated at an expected speed.
As is described above, in cases where the fill-metal is inserted in the semiconductor circuit in addition to the arrangement of wires, the parasitic element expected according to the parasitic element information 102 considerably differs from a parasitic element actually generated in the semiconductor circuit, and there is a problem that an expected performance of the semiconductor circuit is not actually obtained.
An object of the present invention is to provide, with due consideration to the drawbacks of the conventional parasitic element extracting apparatus, a parasitic element extracting apparatus and a parasitic element extracting method in which an extraction precision of information of a parasitic element of a semiconductor circuit is improved in parasitic extraction by considering influence of fill-metal (or dummy wire) inserted in a wiring area of the semiconductor circuit in the designing of a layout of the semiconductor circuit. That is, the information of the parasitic element is extracted from a layout of the semiconductor circuit including a wiring area of a low wire congestion on the assumption that fill-metal is arranged in the wiring area in which the arrangement of the fill-metal is expected.
The object is achieved by the provision of a parasitic element extracting apparatus comprising wire congestion calculating means for calculating a degree of wire congestion in a wiring area, which is placed in a layout of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area, dummy wiring area judging means for pre-setting a reference degree of the wire congestion relating to the arrangement of dummy wire, and comparing the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means with the reference degree of the wire congestion to judge whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated by the wire congestion calculating means, dummy wiring assuming means for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area of the semiconductor circuit calculated by the wire congestion calculating means in cases where it is judged by the dummy wiring area judging means that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area, and parasitic element extracting means for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed by the dummy wiring assuming means is included.
The object is also achieved by the provision of a parasitic element extracting method comprising a wire congestion calculating step for calculating a degree of wire congestion in a wiring area of a semiconductor circuit, according to both the number of wires arranged in the wiring area and the number of wires possible to be arranged in the wiring area, a dummy wiring area judging step for comparing the degree of the wire congestion calculated in the wire congestion calculating step with a reference degree of the wire congestion relating to the arrangement of dummy wire, and judging whether or not dummy wire is arranged in the wiring area for which the degree of the wire congestion is calculated in the wire congestion calculating step, a dummy wiring assuming step for setting an additional amount of the dummy wire according to the degree of the wire congestion in the wiring area calculated in the wire congestion calculating step in cases where it is judged in the dummy wiring area judging step that the dummy wire is arranged in the wiring area, and assuming a circuit layout of the wiring area on condition that the dummy wire, of which the additional amount is set, is arranged in the wiring area, and a parasitic element extracting step for extracting information of a parasitic element of the semiconductor circuit from a layout of the semiconductor circuit in which the circuit layout of the wiring area assumed in the dummy wiring assuming step is included.
Accordingly, because an adverse influence of the dummy wire inserted in the wiring area can be considered in advance when the automatic placement of devices and the automatic routing of wires are performed in the designing of a layout of the semiconductor circuit, the extraction precision of information of the parasitic element can be improved.
It is preferred that information of wire capacitance and/or inductance is extracted as the information of the parasitic element of the semiconductor circuit by the parasitic element extracting means, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set by the parasitic element extracting means to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged. Also, it is preferred that information of wire capacitance and/or inductance is extracted as the information of the parasitic element of the semiconductor circuit in the parasitic element extracting step, a value of the wire capacitance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be higher than a value of the wire capacitance existing in the wiring area in which no dummy wire is arranged, and a value of the inductance, of which the information is extracted from the layout of the semiconductor circuit, is set in the parasitic element extracting step to be lower than a value of the inductance existing in the wiring area in which no dummy wire is arranged.
Accordingly, a difference between an estimated parasitic capacitance and/or inductance and a parasitic capacitance and/or inductance actually existing in the semiconductor circuit can be reduced.
It is preferred that a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates. Also, it is preferred that a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to increase the adjacent wire existence probabilities of the wires of the wiring area at equal rates.
Accordingly, an adverse influence of the dummy wire, which is inserted in the wiring area, can be considered in advance according to a simple assumption operation in the design of the integrated circuit.
It is preferred that a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated by the dummy wiring assuming means according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set by the dummy wiring assuming means, and the circuit layout of the wiring area is assumed by the dummy wiring assuming means so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability. Also, it is preferred that a wire existence probability of the wiring area and a plurality of adjacent wire existence probabilities of wires of the wiring area are calculated in the dummy wiring assuming step according to both a wire existing region and a wiring possible region placed in the wiring area, the additional amount of the dummy wire depending on the degree of the wire congestion in the wiring area is set according to both the wire existence probability of the wiring area and a target wire existence probability of the wiring area pre-set in the dummy wiring assuming step, and the circuit layout of the wiring area is assumed in the dummy wiring assuming step so as to equally increase the adjacent wire existence probabilities of the wires of the wiring area to a fixed adjacent wire existence probability.
Accordingly, an adverse influence of the dummy wire, which is inserted in the wiring area, can be considered in advance according to a simple assumption operation in the design of the integrated circuit.